RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
channel asserts the TPA output. Each channel’s cell buffer availability status (i.e.
the status that will be driven onto the TPA output when the channel is polled) is
deasserted when the first byte of a cell is written into the buffer. It is re-asserted
only after the number of bytes programmed by the associated Downstream
Logical Channel FIFO Ready Level register have been serialized onto a high-
speed link. Determining what value to set the FIFO ready level is discussed in
Section 12.1.
Polling is performed using the TADR[11:0] bus, which supports a 4096 logical
channel address space. Up to 32 logical channels associated with each high-
speed link can be mapped to anywhere within this address space with a
granularity of eight locations through the Logical Channel Base Address
registers. To provide an optimal address map regardless of the number logical
channels per high-speed link, each high-speed link can be programmed to use 8,
16, 24 or 32 address locations through the Logical Channel Address Range
registers. The eight control channels of each S/UNI-VORTEX are mapped to
eight contiguous address locations starting at the address set by the Control
Channel Base Address register. The control channels are associated with the
addresses numerical, i.e. the control channel for TXD0+/- belongs to the lowest
order address and TXD7+/- belongs to the highest order address.
With respect to cell transfers, the Any-PHY port appears like a single PHY entity.
No out of band addressing is required. Instead, the first word of the transferred
cell identifies the destination logical channel. The format of the cell data
structure is illustrated in Fig. 3. As programmed through register bits, a User
Prepend word may be prepended to a basic ATM cell to support applications
where context information is carried inband. By default, only the logical channel
index (Word 0) is prepended.
The cell will be transferred to a S/UNI-VORTEX if the ADDR[11:0] (ADDR[13:12]
is unused in the downstream direction.) field value matches the logical channel
mapping programmed through the Control Channel Base Address, Logical
Channel Base Address and Logical Channel Address Range / Logical Channel
Base Address MSB registers.
Normally, ADDR[11:0] is contained within Word 0 of the Any-PHY data structure,
but can be mapped to the H5/UDF fields. The H5/UDF (User Defined Field) and
User Prepend fields can be handled in four ways:
1. They are excluded from the Any-PHY data structure.
2. They exist in the Any-PHY data structure, but are not passed across the
high-speed serial interfaces. The contents are ignored.
3. They are passed transparently across the high-speed serial interfaces.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
30
PMC [ PMC-SIERRA, INC ]
