RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
S/UNI-DUPLEX to verify that the content of the CRC-32 Accumulator register
is equal to the expected CRC-32 remainder polynomial when the last byte of
the cell is read from the Extract FIFO. The microprocessor can verify the
CRC-32 field check result either through interrupt servicing or polling
techniques.
When interrupt servicing is used, the microprocessor enables the CRC-32
field check prior to reading the last cell of the CPCS-PDU. An interrupt is
raised if a CRC-32 error is found and the EXTCRCERRE bit is set.
When polling is used, the EXTCRCERRE bit is kept to logic 0 and CRC-32
field check is always enabled. The microprocessor verifies the value of the
EXTCRCERRI bit after reading the last cell of a CPCS-PDU.
5. Read the cell content from the Microprocessor Cell Data register. Cell data is
extracted in the format illustrated in Fig. 11.
6. If the cell is not the last of the message, read and store the content of the
Extract CRC-32 Accumulator register. This step is not necessary if the next
cell extracted is known to belong to the same control channel as the current
cell.
The above sequence is repeated as needed to read more cells. The assertion of
the bit of EXTRDY[1:0] of an Extract FIFO indicates that the FIFO is ready again
to be read from. Setting EXTABRT of the Extract FIFO Control register to logic 1
allows the microprocessor to discard a cell without reading the remaining
content.
12.2 Interaction Between Bus and LVDS Configurations
Since the far-end and near-end devices are configured independently it is
important to take into account how the optional fields (the Any-PHY address field,
the H5 (H5/UDF) header bytes, and the user prepend word) are treated on an
end-to-end basis. The following table summarizes the possible cell format
options and summarizes the resultant impact on the cell contents at the receiving
end.
Note the following:
• The S/UNI-DUPLEX’s LVDS links will be connected to other S/UNI-DUPLEX
or to S/UNI-VORTEX devices. The following tables identify registers
appropriate for a S/UNI-DUPLEX to S/UNI-DUPLEX connection. The results
are similar for a S/UNI-DUPLEX to S/UNI-VORTEX. The S/UNI-VORTEX
supports a more limited number of configurations (it does not support 8-bit
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
184
PMC [ PMC-SIERRA, INC ]
