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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
3. Write the cell content to the Microprocessor Cell Data register. Cell data is  
entered in the format illustrated in Fig. 11.  
4. If the cell is not the last of the message, read and store the contents of the  
Insert CRC-32 accumulator register. This step is not necessary if the next cell  
to be inserted belongs to the same control channel as the current cell.  
The above sequence is repeated as needed to insert more cells. The assertion  
of the INSRDY bit of the Insert FIFO indicates that the FIFO is ready again to be  
written to. Setting INSRST of the Insert FIFO Control register to logic 1 prior to  
writing the last cell byte allows the overwriting of the cell data.  
12.1.2 Reading Cell Data From a Control Channel  
Reading cell data from a control channel is done by manipulating the  
Microprocessor Extract FIFO Control and Microprocessor Extract FIFO Ready  
registers. The following steps are required to read a cell from one of the Extract  
FIFOs.  
1. Poll the bit of EXTRDY[1:0] in the Microprocessor Extract FIFO Ready  
registerhigh-speed. The EXTRDY[0] and EXTRDY[1] bits indicate the status  
of the FIFO receiving control channel cells from the RXD1+/- and RXD2+/-  
high-speed links, respectively. Alternately, service the interrupts that result  
from setting the EXTRDYE bit in the Microprocessor Cell Buffer Interrupt  
Control and Status register.  
2. Select the Extract FIFO corresponding to the desired high-speed link by  
writing its identification number to the EXTFSEL bit of the Microprocessor  
Extract FIFO Control register. A logic 0 selects the RXD1+/- FIFO while a logic  
1 selects the RXD2+/- FIFO.  
3. Read the header of the cell to determine if it is the end of message and to  
which virtual channel it belongs.  
4. If CRC-32 protection is required, set the EXTCRCPR of the Microprocessor  
Extract FIFO Control and Status register to logic 0 to enable the CRC-32  
process. The Extract CRC-32 accumulation register can be preset for the first  
cell of a message by writing a logic 1 to EXTCRCPR prior to enable the CRC-  
32 calculation. If the cell is not the first one of a message and does not  
belong to the same control channel as the previous cell read, initialize the  
Extract CRC-32 Accumulator registers to the value saved from the previous  
cell read for the control channel.  
CRC-32 field check is done by setting the EXTCRCCHK bit of the  
Microprocessor Extract FIFO Control register to logic 1. This causes the  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
183  
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