RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x02: Master Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
UPCIFI
OCIF
ICIF
TFI
RFI
TXI
RX2I
RX1I
X
X
X
X
X
X
X
X
RX1I, RX2I:
This register indicates whether there is a pending interrupt for a particular
high-speed serial link receiver. RX1I is associated with RXD1+/-. and RX2I is
associated with RXD2+/-. If RX1I or RX2I is logic 1, at least one interrupt
status bit within the RXD1 or RXD2 High-Speed Serial Interrupt Status
register that has its corresponding enable set is a logic 1.
These bits are not self-clearing; they are only cleared to logic 0 by reading the
RXD1 or RXD2 High-Speed Serial Interrupt Status register.
TXI:
This register indicates whether there is a pending interrupt for the high-speed
serial link transmitter. If TXI is logic 1, the interrupt status bit in the Transmit
High-Speed Serial Cell Count Status register has its corresponding enable set
and is a logic 1.
This bit is not self-clearing; it is only cleared to logic 0 by reading the Transmit
High-Speed Serial Cell Count Status register.
RFI:
This register indicates whether there is a pending interrupt for the Receive
Logical Channel FIFO. IF RFI is logic 1, the interrupt status bit in the Receive
Logical Channel FIFO Interrupt Status register has its corresponding enable
set and is a logic 1.
This bit is not self-clearing; it is only cleared to logic 0 by reading the Receive
Logical Channel FIFO Interrupt register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
88
PMC [ PMC-SIERRA, INC ]
