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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
Register 0x02: Master Interrupt Status  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
R
R
R
R
R
R
R
UPCIFI  
OCIF  
ICIF  
TFI  
RFI  
TXI  
RX2I  
RX1I  
X
X
X
X
X
X
X
X
RX1I, RX2I:  
This register indicates whether there is a pending interrupt for a particular  
high-speed serial link receiver. RX1I is associated with RXD1+/-. and RX2I is  
associated with RXD2+/-. If RX1I or RX2I is logic 1, at least one interrupt  
status bit within the RXD1 or RXD2 High-Speed Serial Interrupt Status  
register that has its corresponding enable set is a logic 1.  
These bits are not self-clearing; they are only cleared to logic 0 by reading the  
RXD1 or RXD2 High-Speed Serial Interrupt Status register.  
TXI:  
This register indicates whether there is a pending interrupt for the high-speed  
serial link transmitter. If TXI is logic 1, the interrupt status bit in the Transmit  
High-Speed Serial Cell Count Status register has its corresponding enable set  
and is a logic 1.  
This bit is not self-clearing; it is only cleared to logic 0 by reading the Transmit  
High-Speed Serial Cell Count Status register.  
RFI:  
This register indicates whether there is a pending interrupt for the Receive  
Logical Channel FIFO. IF RFI is logic 1, the interrupt status bit in the Receive  
Logical Channel FIFO Interrupt Status register has its corresponding enable  
set and is a logic 1.  
This bit is not self-clearing; it is only cleared to logic 0 by reading the Receive  
Logical Channel FIFO Interrupt register.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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