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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
Register 0x00: Master Reset and Identity / Load Performance Meters  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
R
R
R
R
R
R
R
RESET  
TYPE[2]  
TYPE[1]  
TYPE[0]  
ID[3]  
ID[2]  
ID[1]  
ID[0]  
0
0
0
1
0
0
0
1
This register allows the revision number of the S/UNI-DUPLEX to be read by  
software permitting graceful migration to newer, feature-enhanced versions of  
the S/UNI-DUPLEX.  
In addition, writing to this register simultaneously loads all the performance meter  
registers in the S/UNI-DUPLEX.  
ID[3:0]:  
The ID bits can be read to provide a binary S/UNI-DUPLEX revision number.  
TYPE[2:0]:  
The TYPE bits can be read to distinguish the S/UNI-DUPLEX from the other  
members of the S/UNI family of devices.  
RESET:  
The RESET bit allows the S/UNI-DUPLEX to be reset under software control.  
If the RESET bit is a logic one, the entire S/UNI-DUPLEX is held in reset.  
This bit is not self-clearing. Therefore, a logic zero must be written to bring  
the S/UNI-DUPLEX out of reset. Holding the S/UNI-DUPLEX in a reset state  
places it into a low power, stand-by mode. A hardware reset clears the  
RESET bit, thus negating the software reset. Otherwise, the effect of a  
software reset is equivalent to that of a hardware reset.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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