RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x04: Clock Monitor
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
ROOLE
ROOLV
REFCLKA
OFCLKA
IFCLKA
X
X
X
0
X
X
X
X
R/W
R
R
R
R
This register provides activity monitoring of the S/UNI-DUPLEX clocks. When a
monitored clock signal makes a low to high transition, the corresponding register
bit is set high. The bit will remain high until this register is read, at which point,
all the bits in this register are cleared. A lack of transitions is indicated by the
corresponding register bit reading low. This register should be read at periodic
intervals to detect clock failures.
The register also reports the state of the clock synthesis unit that generates the
internal clocks.
IFCLKA:
The IFCLK active (IFCLKA) bit monitors for low to high transitions on the
IFCLK SCI-PHY/Any-PHY interface clock input. IFCLKA is set high on a
rising edge of IFCLK, and is set low when this register is read. When the
Clocked Serial Data interface is used (SCIANY input tied to logic 0), the
IFCLKA bit monitors the internally generated CSDCLK. This clock is
generated by dividing the high-speed serial link clock by 6.
OFCLKA:
The OFCLK active (OFCLKA) bit monitors for low to high transitions on the
OFCLK SCI-PHY/Any-PHY interface clock input. OFCLKA is set high on a
rising edge of OFCLK, and is set low when this register is read. When the
Clocked Serial Data interface is used (SCIANY input tied to logic 0), the
IFCLKA bit monitors the internally generated CSDCLK. This clock is
generated by dividing the high-speed serial link clock by 6.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
92
PMC [ PMC-SIERRA, INC ]
