RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
RESETO:
The RESETO bit controls the state of the RSTOB output. Setting RESETO to
logic 1 causes the active low RSTOB output to be asserted. Setting RESETO
to logic 0 causes the RSTOB output to go back to high impedance. RSTOB
can also be controlled through bit oriented code received on the active high-
speed link.
LRXCINV:
The LRXCINV bit determines the edge of the clock used to sample the
LRXD[15:0] bus. When the LRXCINV bit is set to logic 1, each line of the
LRXD[15:0] bus is sampled on the falling edge of the clock signal input on the
corresponding LRXC[15:0] line. When the LRXCINV bit is set to logic 0, each
line of the LRXD[15:0] bus is sampled on the rising edge of the clock signal
input on the corresponding LRXC[15:0] line.
LTXCINV:
The LTXCINV bit determines the edge of the clock used to output the
LTXD[15:0] bus. When the LTXCINV bit is set to logic 1, each line of the
LTXD[15:0] bus is output on the falling edge of the clock signal input on the
corresponding LTXC[15:0] line. When the LTXCINV bit is set to logic 0, each
line of the LTXD[15:0] bus is output on the rising edge of the clock signal
input on the corresponding LTXC[15:0] line.
Reserved:
These bits must be logic 0 for correct operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
87
PMC [ PMC-SIERRA, INC ]
