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PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
Table 4 Eight Bit SCI-PHY/Utopia Bus Master, Output Configuration  
Byte  
Register 0x14  
INADD  
UDF  
H5  
UDF  
PRE  
LEN  
Notes  
#
bytes  
52  
0
1
2
7
N
N
N
N
N
N
N
Y
X
X
0
1
00  
00  
Short cell, no PHY ID is generated  
Default setting. Utopia compatible,  
standard 53 byte cell, no PHY ID  
1 user byte, H1-H4, no PHY ID  
1 user byte, H1-H5, no PHY ID  
2 user bytes, H1-H4, no PHY ID  
2 user bytes, H1-H5, no PHY ID  
53  
53  
54  
54  
55  
N
N
N
N
Y
Y
Y
Y
N
N
Y
Y
N
Y
N
Y
X
X
X
X
0
1
0
1
01  
01  
10  
10  
Table 5 Sixteen Bit SCI-PHY/Utopia Bus Master, Output Configuration  
Word  
Register 0x14  
INADD  
UDF  
H5  
UDF  
PRE  
LEN  
Notes  
Short cell, no PHY ID  
#
bytes  
52  
54  
54  
0
1
4
N
N
N
N
N
N
Y
Y
N
Y
N
Y
X
X
X
X
0
1
0
1
00  
00  
01  
01  
Default, Utopia compatible, no PHY ID  
2 user bytes, H1-H4, no PHY ID  
56  
2 user bytes, H1-H4, H5/UDF, no PHY ID  
9.1.2 SCI-PHY or Utopia Bus Slave  
The SCI-PHY/Utopia bus slave format is enabled when the IANYPHY,  
OANYPHY, IMASTER, and OMASTER inputs are all tied low.  
In the ingress direction (cells are transferred from the parallel bus input port to  
the LVDS links), the port presents itself as 32 PHY entities but is fully Utopia  
Level 2 compatible when 31 or fewer PHYs are active and IAVALID is tied high.  
Cells read from the bus are queued in a dedicated FIFO for each virtual PHY  
(hereafter referred to as a logical channel). The ability of the FIFOs to accept  
additional cells is discovered through polling using the IADDR[4:0] and IAVALID  
inputs. Upon IAVALID being sampled high the ICA output is asserted if the cell  
FIFO for the logical channel addressed by IADDR[4:0] has at least one empty  
cell buffer. If the FIFO is full, ICA is deasserted. If a cell transfer is in progress  
that will fill a logical channel FIFO, ICA will also be deasserted. If IAVALID is  
sampled low (in SCI-PHY mode) ICA becomes high impedance.  
When operating as a SCI-PHY/Utopia interface, a cell transfer is effected by the  
assertion low of IENB. The logical channel FIFO to which the cell is written is  
selected by the IADDR[4:0] value sampled when IENB was last sampled high.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
51  
 
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