RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
OPRTY
Output
J2
The output port parity (OPRTY) signal completes
the parity (programmable for odd or even parity) of
the ODAT[15:0] bus when OBUS8 is low and the
ODAT[7:0] bus when OBUS8 is high.
The OPRTY signal is updated on the rising edge of
OFCLK.
As a SCI-PHY/Utopia bus master (OMASTER = 1,
OANYPHY = 0) OPRTY is considered valid
coincident with OENB assertion.
As a bus slave (OMASTER = 0) the OPRTY bus is
considered valid only when the S/UNI-VORTEX
device was selected after the polling process and
the OENB signal is sampled low. As an SCI-
PHY/Utopia bus slave (OMASTER = 0, OANYPHY
= 0) OPRTY is driven immediately upon sampling
OENB low, but as an Any-PHY bus slave
(OMASTER = 0, OANYPHY = 1) it has an additional
cycle latency when OANYPHY is logic high. When
not presenting valid data, OPRTY is high
impedance.
As an Any-PHY bus slave autonomous deselection
occurs after the last word of a cell resulting in
setting OPRTY high-impedance until reselection.
This output is only active if the SCIANY input is a
logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
35
PMC [ PMC-SIERRA, INC ]
