欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7350-PGI的Datasheet PDF文件第42页浏览型号PM7350-PGI的Datasheet PDF文件第43页浏览型号PM7350-PGI的Datasheet PDF文件第44页浏览型号PM7350-PGI的Datasheet PDF文件第45页浏览型号PM7350-PGI的Datasheet PDF文件第47页浏览型号PM7350-PGI的Datasheet PDF文件第48页浏览型号PM7350-PGI的Datasheet PDF文件第49页浏览型号PM7350-PGI的Datasheet PDF文件第50页  
RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
Ball  
Name  
Ball  
No. Function  
Type  
High Speed LVDS Links  
OBUS8  
Input  
P4 The output port bus width select (OBUS8) selects  
the output port interface bus width.  
When OBUS8 is high, only ODAT[7:0] present valid  
data and ODAT[15:8] are held low. When OBUS8  
is low, all ODAT[15:0] outputs are used.  
This input is only active if the SCIANY input is a  
logic high.  
OFCLK  
Input  
N5 The output port FIFO clock (OFCLK) is used to  
transfer cells from the internal downstream cell  
buffer to the PHY devices. OFCLK must cycle at a  
52 MHz or lower instantaneous rate, but a high  
enough rate to avoid a FIFO overflow. All SCI-  
PHY/Any-PHY output port timing is relative to the  
rising edge of OFCLK.  
This input is only active if the SCIANY input is a  
logic high.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
31  
 复制成功!