RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
OBUS8
Input
P4 The output port bus width select (OBUS8) selects
the output port interface bus width.
When OBUS8 is high, only ODAT[7:0] present valid
data and ODAT[15:8] are held low. When OBUS8
is low, all ODAT[15:0] outputs are used.
This input is only active if the SCIANY input is a
logic high.
OFCLK
Input
N5 The output port FIFO clock (OFCLK) is used to
transfer cells from the internal downstream cell
buffer to the PHY devices. OFCLK must cycle at a
52 MHz or lower instantaneous rate, but a high
enough rate to avoid a FIFO overflow. All SCI-
PHY/Any-PHY output port timing is relative to the
rising edge of OFCLK.
This input is only active if the SCIANY input is a
logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
31
PMC [ PMC-SIERRA, INC ]
