RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
OCA
I/O
N8 The Output Cell Available (OCA) signal provides
cell-level flow control. OCA’s direction depends on
the state of the OMASTER input.
As a SCI-PHY/Utopia bus master (OMASTER = 1,
OANYPHY = 0) the S/UNI-DUPLEX polls up to 32
PHYs using the PHY address signals OADDR[4:0].
A PHY device being addressed by OADDR[4:0] is
expected to indicate whether or not it can accept a
cell by driving the OCA during the clock cycle
following that in which it is addressed. When a cell
transfer is in progress, the S/UNI-DUPLEX will not
poll the PHY device which is receiving the cell so
PHY devices need not support the cell availability
indication during cell transfer. The selection of a
particular PHY device to which a cell will be written
is indicated by the state of OADDR[4:0] during the
last cycle OENB was high.
As a bus slave (OMASTER = 0) the S/UNI-DUPLEX
indicates the existence of at least one complete cell
within its buffers when polled. The S/UNI-DUPLEX
round-robins between the logical channel cell FIFOs
to autonomously select cells, so the interface
appears as a single PHY slave. When OAVALID is
sampled high in SCI-PHY or low in Any-PHY
configuration and the sampled OADDR[4:0]
matches the OAD[4:0] bits in the Output Address
Match register, OCA is asserted if at least one cell
is available for transfer. If all logical channel FIFOs
are empty, OCA is deasserted. If a cell transfer is in
progress that will read the last available cell, OCA
will also be deasserted. When OAVALID is
sampled low, OCA becomes high impedance. OCA
is delayed by an additional clock cycle in Any-PHY
configuration.
OCA is sampled or updated on the rising edge of
OFCLK.
This signal is only active if the SCIANY input is a
logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
36
PMC [ PMC-SIERRA, INC ]
