RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
Type
No. Function
High Speed LVDS Links
The output port cell data bus (ODAT[15:0]) carries
K3 the ATM cell octets that are transferred to the PHY
K2 devices. Only ODAT[7:0] are used if OBUS8 is
L3 high.
ODAT[15]
ODAT[14]
ODAT[13]
ODAT[12]
ODAT[11]
ODAT[10]
ODAT[9]
ODAT[8]
ODAT[7]
ODAT[6]
ODAT[5]
ODAT[4]
ODAT[3]
ODAT[2]
ODAT[1]
ODAT[0]
Output
J4
(SCIANY
= 1)
L2
M1
M3
The ODAT[15:0] bus is updated on the rising edge
of OFCLK.
As a SCI-PHY/Utopia bus master (OMASTER = 1,
OANYPHY = 0), the ODAT[15:0] bus is considered
valid coincident with OENB assertion.
N2
P2
N4
M4
L5
N6
L6
As a bus slave (OMASTER = 0), the ODAT[15:0]
bus is considered valid only when the S/UNI-
VORTEX device was selected after the polling
process and the OENB signal is sampled low. As an
SCI-PHY/Utopia bus slave (OMASTER = 0,
OANYPHY = 0) ODAT[15:0] is driven immediately
upon sampling OENB low it has an additional
OFCLK cycle latency. When not presenting valid
data, the ODAT[15:0] bus is high impedance.
N7
P7
Autonomous deselection occurs after the last word
of a cell resulting in setting ODAT[15:0] high-
impedance until reselection.
These outputs are only active if the SCIANY input is
a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
PMC [ PMC-SIERRA, INC ]
