RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
IADDR[4]
IADDR[3]
IADDR[2]
IADDR[1]
IADDR[0]
I/O
D6 As a SCI-PHY/Utopia bus master (IMASTER = 1,
A5 IANYPHY = 0) the IADDR[4:0] signals are outputs
D5 used to address up to 32 PHY devices for the
A4 purposes of polling and selection for cell transfer.
C4 When conducting polling, in order to avoid bus
contention, the S/UNI-DUPLEX inserts gap cycles
during which IADDR[4:0] is set to 0x1F and
IAVALID is logic 0. When this occurs, no PHY
device should drive ICA during the following clock
cycle. Polling is performed in incrementing
sequential order. The PHY device selected for
transfer is based on the IADDR[4:0] value present
during the last cycle IENB was high.
As a SCI-PHY/Utopia bus slave (IMASTER = 0,
IANYPHY = 0) IADDR[4:0] are inputs. During
polling when IAVALID is sampled high in SCI-PHY
or low in Any-PHY configuration, the S/UNI-
DUPLEX will drive ICA with the cell buffer
availability status of the logical channel indexed by
IADDR[4:0] on the next IFCLK cycle. The logical
channel selected for a cell transfer is determined by
the IADDR[4:0] value presented when IENB was
last sampled high. Cell transfer is initiated with the
ISOC input being asserted.
As an Any-PHY bus slave (IMASTER = 0, IANYPHY
= 1) IADDR[4:0] are inputs used only for polling. Cell
transfer is initiated with inband addressing (prepend
Word 0 contains the address) and the ISX input.
Polling occurs when IAVALID is sampled low and the
S/UNI-DUPLEX drives ICA with the cell buffer
availability status of the logical channel indexed by
IADDR[4:0]. There is a one IFCLK cycle gap
between IAVALID sampled low and ICA.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
28
PMC [ PMC-SIERRA, INC ]
