RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Clocked Serial Data Interface (Fig. 33)
Symbol
Description
Min
Max
52
Units
LTXC[N], LRXC[N] Frequency
MHz
LTXC[N], LRXC[N] Duty Cycle
40
8
60
%
tS
LRXD[N] Set-up Time to LRXC[N] (see note)
ns
LRXD
tH
LRXD[N] Hold Time to LRXC[N] (see note)
LTXC[N] to LTXD[N] Valid (see note)
5
1
ns
ns
LRXD
LTXD
tP
13
Note:
Polarity of the active edge of LTXC[N] and LRXC[N] is determined by the
respective value of the LRXCINV and LTXCINV bits in the Master Configuration
register.
Fig. 33: Clocked Serial Data Interface
LRXC[N]
tH
tS
LRXD
LRXD
LRXD[N]
LTXC[N]
tP
LTXD
LTXD[N]
High-Speed Serial Interface
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
224
PMC [ PMC-SIERRA, INC ]
