RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Registers 0x44, 0x54:
RXD1, RXD2 High-Speed Serial HCS Error Count
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
HCSERR[7]
HCSERR[6]
HCSERR[5]
HCSERR[4]
HCSERR[3]
HCSERR[2]
HCSERR[1]
HCSERR[0]
X
X
X
X
X
X
X
X
HCSERR[7:0]:
If any of the CELLCRC, CNTCELLERR, and PREPEND bits of the Receive
High-Speed Serial Configuration register is logic 0, the HCSERR[7:0] bits
indicate the number of HCS error events while in the SYNC cell delineation
state that occurred during the last accumulation interval on the associated
RXD1+/- or RXD2+/-link.
If the CELLCRC, CNTCELLERR, and PREPEND bits are logic 1, the
HCSERR[7:0] bits indicate the number of cells with non-zero cell CRC-8 or
HCS remainders while in the SYNC cell delineation state. (Simultaneous non-
zero cell CRC-8 and HCS remainders result in a single increment).s.
The contents of this register become valid a maximum of 300 ns after a
transfer is triggered by a write to this register, one of the associated (i.e. this
link only) Receive High-Speed Serial Cell Counter registers or the Load
Performance Meters (0x00) register, and remain valid until another transfer is
triggered.
The count saturates at all ones.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
148
PMC [ PMC-SIERRA, INC ]
