RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Registers 0x42, 0x52:
RXD1, RXD2 High-Speed Serial Interrupt Enables
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
HCSE
X
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XFERE
OCDE
CELLERRE
ACTE
LCDE
LOSE
These registers allow changes in the corresponding RXD1 High-Speed Serial
Cell Filtering Configuration/Status and RXD2 High-Speed Serial Cell Filtering
Configuration/Status register bits, HCS errors and counter transfers to cause
assertion low the INTB output.
The Master Interrupt Enable bit of the Master Configuration register must also be
logic 1 for the interrupt enables to take effect.
LOSE:
The LOSE bit enables the generation of an interrupt upon a change in the
Loss of Signal state. When LOSE is set to logic 1, the INTB output is
asserted low when the LOSI bit is logic 1.
LCDE:
The LCDE bit enables the generation of an interrupt due to a change in the
LCD (Loss of Cell Delineation) state. When LCDE is set to logic 1, the INTB
output is asserted low when the LCDI bit is logic 1.
ACTE:
The ACTE bit enables the generation of an interrupt due to a change in the
ACTV register bit. When ACTE is set to logic 1, the INTB output is asserted
low when the ACTI bit is logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
144
PMC [ PMC-SIERRA, INC ]
