RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
CELLERRE:
The CELLERRE bit enables the generation of an interrupt due to a non-zero
remainder of the CRC-8 protecting the entire cell while in the SYNC cell
delineation state. When CELLERRE , CELLCRC, and PREPEND are set to
logic 1, the interrupt is enabled.
OCDE:
The OCDE bit enables the generation of an interrupt due to a change in cell
delineation state. When OCDE is set to logic 1, the INTB output is asserted
low when the OCDI bit is logic 1.
HCSE:
The HCSE bit enables the generation of an interrupt due to the detection of a
HCS error while in the SYNC cell delineation state. When HCSE is set to
logic 1, the INTB output is asserted low when the HCSI bit is logic 1.
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation
interval is completed and new values are stored in the receive cell counter
and HCS error counter holding registers. When XFERE is set to logic 1, the
INTB output is asserted low when the XFERI bit is logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
145
PMC [ PMC-SIERRA, INC ]
