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PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
CELLERRE:  
The CELLERRE bit enables the generation of an interrupt due to a non-zero  
remainder of the CRC-8 protecting the entire cell while in the SYNC cell  
delineation state. When CELLERRE , CELLCRC, and PREPEND are set to  
logic 1, the interrupt is enabled.  
OCDE:  
The OCDE bit enables the generation of an interrupt due to a change in cell  
delineation state. When OCDE is set to logic 1, the INTB output is asserted  
low when the OCDI bit is logic 1.  
HCSE:  
The HCSE bit enables the generation of an interrupt due to the detection of a  
HCS error while in the SYNC cell delineation state. When HCSE is set to  
logic 1, the INTB output is asserted low when the HCSI bit is logic 1.  
XFERE:  
The XFERE bit enables the generation of an interrupt when an accumulation  
interval is completed and new values are stored in the receive cell counter  
and HCS error counter holding registers. When XFERE is set to logic 1, the  
INTB output is asserted low when the XFERI bit is logic 1.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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