RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Registers 0x43,0x53:
RXD1, RXD2 High-Speed Serial Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
OVR
XFERI
HCSI
X
X
X
X
X
X
X
X
OCDI
CELLERRI
ACTI
LCDI
LOSI
These registers provide an indication of events that have occurred since the last
time they were read. These bits are not affected by the programming of the
RXD1 and RXD2 High-Speed Serial Interrupt Enables registers, which only
determines whether the status of the bits in these registers is propagated to the
INTB output.
LOSI:
The LOSI bit is set to logic 1 whenever the associated LOSV register bit
changes state. This bit is reset immediately after a read to this register.
LCDI:
The LCDI bit is set to logic 1 whenever the associated LCDV register bit
changes state. This bit is reset immediately after a read to this register.
ACTI:
The ACTI bit is set to logic 1 whenever the associated ACTV register bit
changes state. This bit is reset immediately after a read to this register.
CELLERRI:
The CELLERRI bit is set high when a non-zero remainder occurs for the
CRC-8 protecting the entire cell. This bit is reset immediately after a read to
this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
146
PMC [ PMC-SIERRA, INC ]
