RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Registers 0x41, 0x51:
RXD1, RXD2 High-Speed Serial Cell Filtering Configuration/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
HCSPASS
Reserved
OCDV
X
0
R/W
R/W
R
0
X
X
X
X
X
Unused
ACTV
R
R
R
LCDV
LOSV
These registers provide the status of each individual RXD1+/- and RXD2+/- serial
link.
LOSV:
The LOSV gives the Loss of Signal state. LOSV becomes logic 1 upon 2048
bit periods (13.2 μs at 155.52 Mb/s) without a signal transition in the received
data (i.e. before descrambling, if enabled). LOSV becomes logic 0 when a
signal transition has occurred in each of 16 consecutive non-overlapping
intervals of 16 bit periods each.
LCDV:
The LCDV bit gives the Loss of Cell Delineation state. When LCDV is logic 1,
an out of cell delineation (OCD) defect has persisted for 1318 cells. LCDV
becomes logic 0 when cell delineation has been maintained for 1318 cells.
LCDV is logic 1 out of reset.
ACTV:
The ACTV bit provides the debounced state of the ACTIVE bit in the cell
prepend. ACTV reflects the state of the ACTIVE bit when it has been the
same for three consecutive valid cells.
OCDV:
The OCDV bit indicates the cell delineation state. When OCDV is logic 1, the
cell delineation state machine is in the 'HUNT' or 'PRESYNC' states and is
hunting for the cell boundaries. When OCDV is logic 0, the cell delineation
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
142
PMC [ PMC-SIERRA, INC ]
