RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Registers 0x40, 0x50:
RXD1, RXD2 High-Speed Serial Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
DDSCR
HDSCR
0
1
X
0
0
0
1
0
Unused
R/W
R/W
R/W
R/W
R/W
CNTCELLERR
CELLCRC
PREPEND
USRHDR[1]
USRHDR[0]
These registers configure, on a per-link basis, the format of the cells expected on
RXD1 and RXD2 serial links.
USRHDR[1:0]:
The USRHDR[1:0] bits determine the length of the expected User Header
field of the received cells, as illustrated in Fig. 9.
USRHDR[1:0] Bytes in User Header
00
01
10
11
4
5
6
Reserved
PREPEND:
The PREPEND bit determines if the User Prepend field is expected to exist in
the received cells. If PREPEND is logic 1, a two byte User Prepend is
expected to follow the System Prepend field.
CELLCRC:
The CELLCRC bit determines whether the entire high-speed serial data
structure is expected to be protected by a CRC-8 code word. The PREPEND
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
140
PMC [ PMC-SIERRA, INC ]
