S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
CTSCLK_SEL
When CTSCLK_SEL is set and LINE_MODE=”1”, the CTSCLK pin is used as the clock
for all Transmit Serial Line Clocks. When CTSCLK_SEL is not set and
LINE_MODE=”1”, the TSCLK[3:0] pins are used for all Transmit Serial Line Clocks.
MAX_DCB_DEPTH
This indicates the number of cells that can be stored for a single link in the external
SDRAM. This determines the number of bits the RDAT will use for the read and write
pointers. This bit should be set to a ‘1’ for the S/UNI-IMA-4 device.
0) 256 cells per link.
1) 1024 cells per link.
CHAN_CD
This indicates that the channelized cell delineation may be used. Channelized cell
delineation results in faster cell delineation since an octet-by-octet search is performed
instead of a bit by bit search. This option may only be used when operating the clk/data
interface in channelized mode. If any links are operating in unchannelized mode, this bit
may not be set.
0) Use bit by bit search for cell delineation. (Safe mode).
1) Use octet or nibble search for cell delineation (only should be set if operating with
channelized line interface for all links).
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
99
PMC [ PMC-SIERRA, INC ]
