S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
RDAT_INTR
When set, there is an interrupt pending from the RDAT block. Read the
RDAT_INTR_STATUS_REG located in register 0x310 to determine the cause of the
interrupt. This bit indicates current status and will clear only when no interrupt conditions
remain in RDAT_INTR_STATUS_REG. On read:
0) No interrupt pending from the RDAT block.
1) Interrupt pending from the RDAT block.
ICP_CELL_AVL
When set, it indicates that a new ICP Cell is available in the RIPP Forwarding ICP cell
buffer. The RIPP Forwarding ICP cell buffer can be used to extract ICP cells for a group.
This bit is cleared when register 0x230 ICP Cell Forwarding Status is read.
0) No ICP cell is available.
1) An ICP cell is available in the RIPP Forwarding ICP buffer.
MISC_INTR
When set, it indicates that an interrupt is pending in the Miscellaneous Interrupt Register
located in register 0x00A. This bit indicates current status, and will clear only when no
interrupt conditions exist in the Miscellaneous Interrupt register. On read:
0) No Miscellaneous interrupt pending.
1) Miscellaneous interrupt pending.
TC_INTR
When set, indicates that a TC layer is pending in the Receive TC Interrupt FIFO. This bit
indicates current status and will clear only when the Receive TC Interrupt FIFO is empty.
0) No TC Interrupts in the Receive TC Interrupt FIFO.
1) TC Interrupts are present in the Receive TC Interrupt FIFO.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
102
PMC [ PMC-SIERRA, INC ]
