S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
11.2 Master Interrupt Registers
Register 0x008: Master Interrupt Register
Bit
15:9
8
7
6:4
3
2
1
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
Function
Unused
TC_INTR
MISC_INT
Reserved
ICP_CELL_AVL
RDAT_INTR
TIMA_INTR
RIPP_INTR
Default
0
0
0
0
0
0
0
0
This register is the top of the Interrupt Tree. It indicates which lower level interrupt registers
have interrupts pending. Note that the respective bits will remain set as long as the underlying
condition remains active.
RIPP_INTR
When set, there is an interrupt pending from the RIPP block. Read the RIPP_INTR_FIFO
located in Register 0x216 to determine the group that caused the interrupt. This bit indicates
current status and will clear only when RIPP_INTR_FIFO is empty. On read:
0) No interrupt pending from the RIPP block.
1) Interrupt pending from the RIPP block.
TIMA_INTR
When set, there is an interrupt pending from the TIMA block. Read the
TIMA_OVERFLOW_REG located in register 0x328 to determine the cause of the
interrupt. This bit indicates current status and will clear only when no interrupt conditions
remain in TIMA_OVERFLOW_REG. On read:
0) No interrupt pending from the TIMA block.
1) Interrupt pending from the TIMA block.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
101
PMC [ PMC-SIERRA, INC ]
