S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
7
Description
The PM7348 S/UNI-IMA-4 is a monolithic integrated circuit that implements the Inverse
Multiplexing for ATM (IMA 1.1) with backward compatibility to IMA 1.0 and the Transmission
Convergence (TC) layer function. The S/UNI-IMA-4 supports 4 independent T1, E1 or
unchannelized links. Each link is dynamically configurable to support either IMA 1.1, backward
compatible IMA 1.0, or ATM HEC cell delineation. ATM over Fractional T1/E1 is also
supported. Unchannelized links may be used to support applications such as G.SHDSL or
ADSL.
All links within an IMA group must be the same nominal rate as required by the IMA
specification, however the link rates within a group can be different across groups.
IMA is a protocol designed to combine the transport bandwidth of multiple links into a single
logical link. The logical link is called a group. The S/UNI-IMA-4 can support up to 4
independent groups with each group capable of supporting a maximum of all available links.
Any link that is not participating in an IMA group can utilize the cell delineation features of the
S/UNI-IMA-4 for implementing either ATM over T1/E1 or ATM over xDSL.
In the transmit direction, the S/UNI-IMA-4 accepts cells from the Any-PHY/UTOPIA Interface.
The S/UNI-IMA-4 performs the IMA function that consists of taking a cell stream destined for a
group and distributing the cells in a round-robin fashion to the links within a group, adding IMA
Control Protocol (ICP) cells, filler cells, and stuff cells as needed. The ICP cells convey state
information to the far end and are used to format an IMA frame. The IMA Frame is used as a
mechanism to synchronize the links at the far end. Cell rate decoupling is performed at the IMA
sub-layer via filler cells. Filler cells are used instead of physical layer cells for cell rate
decoupling, thus a continuous stream of cells is sent to the TC layer. The stuff cells are used to
maintain synchronization between the links in a group by absorbing the rate differential when
links are running on different clocks.
The data from the IMA sub-layer is passed on to the TC layer. In the TC layer, the HEC is
calculated and inserted into the cell headers and optional scrambling of the payload is
performed. The cell stream is then mapped into the T1 or E1 payload with zeros inserted for the
framing and overhead bits or bytes.
The links are then transmitted via the serial interfaces. The clock is provided from each serial
clock pin. An optional common-clock mode is provided to enable all links to run from the same
clock.
On the receive side, the data is received from the clock/data interface. The TC layer searches for
cell delineation as per the procedures outlined in ITU-T Recommendation I.432.1. Once cell
delineation is obtained, the payload is optionally descrambled and the cells are passed to the
IMA sub-layer. The TC layer provides counts of errored headers as well as OCD and LCD error
interrupts.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
27
PMC [ PMC-SIERRA, INC ]
