S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
The timing relationship of the transmit clock (TSCLK[n]) and data (TSDATA[n]) signals of a
channelized T1 link is shown in Figure 38. The transmit data stream is a T1 frame with a single
framing bit (F in Figure 38) followed by octet bound time-slots 1 to 24. TSCLK[n] is held
quiescent during the framing bit. The most significant bit of each time-slot is transmitted first
(B1 in Figure 38). The least significant bit of each time-slot is transmitted last (B8 in Figure 38).
The TSDATA[n] bit (B8 of TS24) before the framing bit is the least significant bit of time-slot
24. In Figure 38, the quiescent period is shown to be a low level on TSCLK[n]. A high level,
affected by extending the high phase of bit B8 of time-slot TS24, is equally acceptable. In
channelized T1 mode, TSCLK[n] can only be gapped during the framing bit. It must be active
continuously at 1.544 MHz during all time-slot bits. Time-slots that are not provisioned to
belong to any channel (the PROV bit in the corresponding word of the transmit channel
provision RAM in the TCAS block set low) transmit the contents of the Idle Fill Time-slot Data
register.
Figure 38 Channelized T1 Transmit Link Timing w/ Clock gapped Low
TSCLK[n]
B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
TSDATA[n]
TS 24
F
TS 1
TS 2
Figure 39 Channelized T1 Transmit Link Timing w/ Clock gapped high
TSCLK[n]
B7 B8
TS 24
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
B1
TSDATA[n]
F
TS 1
TS 2
The timing relationship of the transmit clock (TSCLK[n]) and data (TSDATA[n]) signals of a
channelized E1 link is shown in Figure 40. The transmit data stream is an E1 frame with a
single framing byte (FAS/NFAS in Figure 40) followed by octet bound time-slots 1 to 31.
TSCLK[n] is held quiescent during the framing byte. The most significant bit of each time-slot
is transmitted first (B1 in Figure 40). The least significant bit of each time-slot is transmitted
last (B8 in Figure 40). The TSDATA[n] bit (B8 of TS31) before the framing byte is the least
significant bit of time-slot 31. In Figure 40, the quiescent period is shown to be a low level on
TSCLK[n]. A high level, affected by extending the high phase of bit B8 of time-slot 31, is
equally acceptable. In channelized E1 mode, TSCLK[n] can only be gapped during the framing
byte. It must be active continuously at 2.048 MHz during all time-slot bits. Time-slots that are
not provisioned to belong to any channel − i.e., the PROV bit in the corresponding word of the
transmit channel provision RAM in the TCAS block is set low − transmit the contents of the
Idle Time-slot Fill Data register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
296
PMC [ PMC-SIERRA, INC ]
