S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
14 Functional Timing
14.1 Receive Link Input Timing
The timing relationship of the receive clock (RSCLK[n]) and data (RSDATA[n]) signals of an
unchannelized link is shown in Figure 34. The receive data is viewed as a contiguous serial
stream. There is no concept of time-slots in an unchannelized link. Each eight bits is grouped
together into a byte with arbitrary alignment. The first bit received (B1 in Figure 34) is deemed
the most significant bit of an octet. The last bit received (B8) is deemed the least significant bit.
Bits that are to be processed by the S/UNI-IMA-4 are clocked in on the rising edge of
RSCLK[n]. Bits that should be ignored (X in Figure 34) are squelched by holding RSCLK[n]
quiescent. In Figure 34, the quiescent period is shown to be a low level on RSCLK[n]. A high
level, affected by extending the high phase of the previous valid bit, is also acceptable.
Selection of bits for processing is arbitrary and is not subject to any byte alignment or frame
boundary considerations.
Figure 34 Unchannelized Receive Link Timing
RSCLK[n]
B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X
RSDATA[n]
The timing relationship of the receive clock (RSCLK[n]) and data (RSDATA[n]) signals of a
channelized T1 link is shown in Figure 35. The receive data stream is a T1 frame with a single
framing bit (F in Figure 35) followed by octet bound time-slots 1 to 24. RSCLK[n] is held
quiescent during the framing bit. The RSDATA[n] data bit (B1 of TS1) clocked in by the first
rising edge of RSCLK[n] after the framing bit is the most significant bit of time-slot 1. The
RSDATA[n] bit (B8 of TS24) clocked in by the last rising edge of RSCLK[n] before the
framing bit is the least significant bit of time-slot 24. In Figure 35, the quiescent period is
shown to be a low level on RSCLK[n]. A high level, affected by extending the high phase of bit
B8 of time-slot TS24, is equally acceptable. In channelized T1 mode, RSCLK[n] can only be
gapped during the framing bit. It must be active continuously at 1.544 MHz during all time-slot
bits. Time-slots can be ignored by setting the PROV bit in the corresponding word of the receive
channel provision RAM in the RCAS block to low.
Figure 35 Channelized T1 Receive Link Timing
RSCLK[n]
B7 B8 F B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
RSDATA[n]
TS 24
TS 1
TS 2
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
294
PMC [ PMC-SIERRA, INC ]
