S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x180: TCAS Indirect Link and Time-slot Control Register
Bit
15
Type
RO
Function
Busy
Default
X
14
R/W
RWB
0
13:10
9:8
7:5
4:0
Unused
LINK[1:0]
Unused
TSLOT[4:0]
X
0
X
0
R/W
R/W
This register provides the link number and time-slot number used to access the timeslot
provision RAM. Writing to this register triggers an indirect register access and transfers the
contents of the Indirect Link Data register to an internal holding register.
TSLOT[4:0]
The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be configured or
interrogated in the indirect access. For a channelized T1 link, time-slots 1 to 24 are valid.
For a channelized E1 link, time-slots 1 to 31 are valid. For unchannelized links, only time-
slot 0 is valid.
LINK[1:0]
The indirect link number bits (LINK[1:0]) select amongst the 4 transmit links to be either
configured or interrogated in the indirect access.
RWB
The indirect access control bit (RWB) selects between a configure (write) or interrogate
(read) access to the timeslot provision RAM. The address to the timeslot provision RAM is
constructed by concatenating the TSLOT[4:0] and LINK[1:0] bits. Writing a logic zero to
RWB triggers an indirect write operation. Data to be written is taken from the PROV and
the VLINK[1:0] bits of the Indirect Data register. Writing a logic one to RWB triggers an
indirect read operation. Addressing of the RAM is the same as in an indirect write
operation. The data read can be found in the PROV and the VLINK[1:0] bits of the Indirect
Link Data register after the BUSY bit has cleared.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
142
PMC [ PMC-SIERRA, INC ]
