S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x106: RCAS Link Disable
Bit
15
14:2
1:0
Type
R
Function
VLDIS
Unused
Default
0
X
0
R/W
DVLINK[1:0]
This register allows the squelching of output data from a particular virtual link.
DVLINK[1:0]
The disable virtual link bits (DVLINK[1:0]) specify the virtual link whose output data from
the RCAS are to be squelched. When VLDIS is set high, the virtual link specified by
DVLINK[1:0] is disabled, even if the virtual link is provisioned.
VLDIS
When set high, the virtual link disable bit (VLDIS) squelches valid data on the output of
RCAS for the virtual link indicated by DVLINK[1:0].
Register 0x140- 0x14E: RCAS Link #0 to Link #3 Configuration
Bit
15:3
2
1
0
Type
R
R/W
R/W
R/W
Function
Unused
Reserved
E1
Default
X
0
0
0
CEN
This register configures operational modes of receive link #0 to link #3 (RSDATA[N]/
RSCLK[N] where 0 ? N ? 3).
CEN
The channelize enable bit (CEN) configures link #N for channelized operation.
When CEN=1, RSCLK[N] must be gapped during the T1 framing bit and during the E1
framing byte. The data bit on RSDATA[N] that is clocked in by the first rising edge of
RSCLK[N] after an extended low period is considered to be the most significant bit of time-
slot 1.
When CEN=0, link #N is unchannelized. The E1 register bit is ignored. RSCLK[N] must be
gapped during non-data bits. All data bits are treated as a contiguous stream with arbitrary
byte alignment.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
140
PMC [ PMC-SIERRA, INC ]
