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PM7348 参数 Datasheet PDF下载

PM7348图片预览
型号: PM7348
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM/SONET/SDH IC, CMOS, PBGA324,]
分类和应用: ATM异步传输模式
文件页数/大小: 318 页 / 1736 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI-IMA-4 Telecom Standard Product Data Sheet  
Released  
Register 0x102: RCAS Indirect Link Data Register  
Bit  
15:10  
9
Type  
R
R/W  
R/W  
Function  
Unused  
VLDLBEN  
PROV  
Default  
X
0
0
8
7:2  
1:0  
Unused  
VLINK[1:0]  
X
00  
R/W  
The RCAS Timeslot Provision RAM maps either timeslots from a physical link or an entire  
physical link to a Virtual Link. It also provisions timeslots/links and enables Diagnostic  
Loopback.  
This register contains either: (1) the data read from the RCAS Timeslot Provision RAM after an  
indirect read operation or (2) the data to be inserted into the RCAS Timeslot Provision RAM  
during an indirect write operation.  
VLINK[1:0]  
VLINK[1:0] is the Virtual Link to which this RCAS LINK/TSLOT is mapped. Valid values  
are 0x0 to 0x3. For proper operation, timeslots from multiple physical links cannot be  
mapped to the same VLINK.  
After an indirect read operation has been completed, VLINK[1:0] reports the virtual link  
number read from the RCAS Timeslot Provision RAM. The Virtual Link number to be  
written to the RCAS Timeslot Provision RAM in an indirect write operation must be set up  
in this register before triggering the write. VLINK[1:0] reflects the value written until the  
completion of a subsequent indirect read operation.  
PROV  
The indirect provision enable bit (PROV) reports the timeslot provision enable flag read  
from the timeslot provision RAM after an indirect read operation has been completed. The  
provision enable flag to be written to the timeslot provision RAM in an indirect write  
operation must be set up in this register before triggering the write. When PROV is set high,  
the current receive data byte is processed as part of the virtual link (as indicated  
VLINK[1:0]). When PROV is set low, the current time-slot does not belong to any virtual  
link and the receive data byte is ignored. PROV reflects the value written until the  
completion of a subsequent indirect read operation.  
VLDLBEN  
When the indirect virtual link based diagnostic loopback enable bit VLDLBEN=1, the  
current receive data byte will be over-written by a data byte retrieved from the loopback  
FIFO of the Virtual Link as indicated by VLINK[1:0]. When VLDLBEN=0, the current  
receive data byte is processed normally.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2020889, Issue 2  
137  
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