S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
HCSPASS
The HCSPASS bit controls the dropping of cells based on the detection of an HCS error.
When HCSPASS is logic 0, cells containing an HCS error are dropped. When HCSPASS is
a logic 1, cells are passed to the Receive IMA Data Processor regardless of errors detected
in the HCS. For IMA links, this bit must be set to a logic 1 to allow for proper IFSM
operation. All HCS errored cells will always be dropped by the Receive IMA Data
Processor (regardless of the mode). For TC-only links, the HCSPASS bit has no effect.
LCDOOCDPASS
The LCDOCDPASS bit controls the dropping of cells based on the detection of an out of
cell delineation and loss of cell delineation. When LCDOOCDPASS is logic 0, cells
containing an OOCD error and an LCD error are dropped. When LCDOOCDPASS is a
logic 1, cells are passed to the Receive IMA Data Processor regardless of errors detected in
the OOCD and LCD. For IMA links, this bit must be set to a logic 1 to allow for proper
IFSM operation (the Receive IMA Data Processor will drop these cells). For TC-only links,
the Receive IMA Data Processor will drop cells with OCD, but will not drop good cells
received during LCD after OCD has exited. Therefore, for TC-only mode, LCDOCDPASS
should be set to a logic 0.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
130
PMC [ PMC-SIERRA, INC ]
