S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x070: RTTC Indirect Link Control Register
Bit
15
14
13
12:2
1:0
Type
R
R/W
R/W
Function
LBUSY
LRWB
DRHCSE
Reserved
LINK[1:0]
Default
0
0
0
0
0
R/W
This register provides the link number used to access the RTTC link provision RAM. Writing
to this register triggers an indirect link-register access.
LINK[1:0]
LINK[1:0] is used to specify the link to be configured or interrogated in the indirect link
access. Only 4 links are available. Valid values for the LINK field should range from 0x0
to 0x3.
DRHCSE
Disable Reset of the HCS Error Count (DRHCSE) disables automatic reset of the HCS
Error Counter (HCSERR). When the bit is set to logic 0, automatic reset of the HCS Error
Counter is enabled. If an indirect read is initiated (i.e., CRWBs written with logic 1) with
DRHCSE logic 0, the HCS Error Counter is reset to zero upon completion of the indirect
read. When the DRHCSE bit is set to logic 1, automatic reset of the HCS Error Counter is
disabled.
An indirect read results in the interrupt status, as well as the HCSERR count, being read
(and possibly cleared). In this situation, the DRHCSE bit is useful for separating interrupt
processing from HCSERR count accumulation because it can disable the HCSERR count
reset when querying for interrupts.
LRWB
The Link indirect access control bit (LRWB) selects between a configure (write) or
interrogate (read) access to the Link context RAM. Writing a logic 0 to LRWB triggers an
indirect write operation. Data to be written is taken from the Indirect Link Data registers.
Writing a logic 1 to LRWB triggers an indirect read operation. The read data can be found
in the Indirect Link Data registers.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
126
PMC [ PMC-SIERRA, INC ]
