S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x074: RTTC Indirect Link Interrupt and Status Register
Bit
15:6
5
4
3
2
1
0
Type
Function
Unused
OOCDV
LCDV
OOCDI
HCSI
Default
R
R
R
R
R
R
1
0
0
0
0
0
FOVRI
LCDI
This register contains data read from the RTTC Link provision RAM after an indirect read
operation.
LCDI
The LCDI bit is set high when there is a change in the loss of cell delineation (LCD) state.
This bit is reset immediately after a read to this register. Note that the state of the Receive
TC Interrupt FIFO is independent of this bit (clearing on read will not affect the FIFO
behavior).
FOVRI
The FOVRI bit is set to logic 1 when a FIFO overrun occurs. This bit is reset immediately
after a read to this register. Note that the state of the Receive TC Interrupt FIFO is
independent of this bit (clearing on read will not affect the FIFO behavior).
HCSI
The HCSI bit is set high when an HCS error is detected. This bit is reset immediately after a
read to this register. Note that the state of the Receive TC Interrupt FIFO is independent of
this bit (clearing on read will not affect the FIFO behavior).
OOCDI
The OOCDI bit is set high when the logical Link enters or exits the SYNC state. The
OOCDV bit indicates whether the logical Link is in the SYNC state or not. The OOCDI bit
is reset immediately after a read to this register. Note that the state of the Receive TC
Interrupt FIFO is independent of this bit (clearing on read will not affect the FIFO
behavior).
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
131
PMC [ PMC-SIERRA, INC ]
