S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
11.5 TC Layer Registers
Register 0x060: TTTC Indirect Link Control Register
Bit
15
14
13:2
1:0
Type
R
R/W
Function
LBUSY
LRWB
Reserved
LINK[1:0]
Default
0
0
0
0
R/W
This register provides the link number used to access the TTTC link provision RAM. Writing to
this register triggers an indirect link register access.
LINK[1:0]
LINK[1:0] is used to specify the link to be configured or interrogated in the indirect link
access. Only 4 links are available. Valid values for the LINK field should range from 0x0
to 0x3.
LRWB
The link indirect access control bit (LRWB) selects between either a configure (write) or
interrogate (read) access to the link-context RAM. Writing a logic 0 to LRWB triggers an
indirect write operation. Data to be written is taken from the Indirect Link Data registers.
Writing a logic 1 to LRWB triggers an indirect read operation. The read data can be found
in the Indirect Link Data registers.
LBUSY
The indirect link access status bit (LBUSY) reports the progress of an indirect access A
write to the Indirect Link Address register triggers an indirect access and sets LBUSY to
logic 1; it will remain logic 1 until the access is complete. This register should be polled to
determine either: (1) when data from an indirect read operation is available in the Indirect
Link Data registers or (2) when a new indirect write operation may commence. The LBUSY
is not expected to remain at logic 1 for more than 86 REFCLK cycles.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
124
PMC [ PMC-SIERRA, INC ]
