Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
4.3.3 Switch Element Interface Signals
Table 10. Switch Element Interface Signals (47 Pins)
Drive/
Input Level
Slew
Rate
Signal Name
SE_CLK
Ball
Type
Description
AA26
In
CMOS
Switch Element Clock is the 50 MHz or
66 MHz clock for nibble transfer.
RX_CELL_START
BP_ACK_IN(3:0)
SE_SOC_OUT
W28
In
In
5 V or LV
TTL
Receive Cell Start indicates the SOC time in
the receive direction. It should be driven high
every cell time (118 SE_CLKs).
R27, U29,
U28, T28
5 V or LV
TTL
Backpressure Input 3 down to 0. It carries the
cell acknowledge and backpressure from the
switch fabric.
L27
Out
8 ma
Mod Switch Fabric Start Of Cell Out indicates the
SOC for all four SE_D_OUT signals. This sig-
nal precedes the first nibble of cell by one
clock. For cells leaving the QRT and entering
the switch fabric, this signal indicates the SOC.
SE_D_OUT0(3:0)
SE_D_OUT1(3:0)
SE_D_OUT2(3:0)
SE_D_OUT3(3:0)
BP_ACK_OUT(3:0)
P25, R28,
R25, R26
Out
Out
Out
Out
Out
5 ma
5 ma
5 ma
5 ma
8 ma
Mod Switch Element Data Out Ports 3 down to 0
Bits 3 down to 0 are four nibble-wide pathways
that carry the cell to the QSEs (PM73488).
N28, P28,
P26, P27
Mod
N27, M26,
N29, M27
Mod
Mod
L26, N26,
M28, L28
U27, T27,
U26, V28
Mod Backpressure Output 3 down to 0 asserts mul-
tipriority backpressure and cell acknowledge
toward the switch fabric.
SE_SOC_IN(3:0)
V26, T25,
V25, U25
In
5 V or LV
TTL
Switch Fabric Start of Cell 3 to 0 indicates the
SOC time in the transmit direction for the four
incoming SE_D_IN3, SE_D_IN2, SE_D_IN1
and SE_D_IN0, respectively.
SE_D_IN0(3:0)
SE_D_IN1(3:0)
SE_D_IN2(3:0)
SE_D_IN3(3:0)
AB26, AA25,
AC28, AD28
In
In
In
In
5 V or LV
TTL
Switch Element Data In Ports 3 to 0 Bits 3
down to 0 are part of the nibble-wide, 50 MHz
data pathway that carries the cell from the
switch fabric.
AB27, Y26,
AD29, AB28
5 V or LV
TTL
W26, Y25,
Y27, W25
5 V or LV
TTL
W27, AA28,
AA27, Y28
5 V or LV
TTL
65
PMC [ PMC-SIERRA, INC ]
