Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
3 FAULT TOLERANCE
3.1 The Data Path
Figure 48 shows the basic data path through the switch. The SE_D_OUT/IN and SE_SOC_OUT/
IN signals are used in the forward path, and the BP_ACK_OUT/IN signals are used in the back-
ward path. Data enters the switch via the ingress or receive side UTOPIA interface and is queued
at the Input half of the QRT (the IRT). The receive queue controller selects cells that are then
played out to the switch fabric, which consists of one or more stages of QSEs. The cell finally
enters the egress QRT where it is queued again at the Output half of the QRT (the ORT). The
transmit queue controller selects a cell which is then played out of the switch via the egress or
transmit side UTOPIA interface.
UTOPIA
Interface
QRT/QSE
Interface
QSE/QRT
Interface
UTOPIA
Interface
QRT
(ORT Portion)
QRT
(IRT Portion)
g
h
a
b
A
A
c
d
c
d
e
f
e
f
QSE
(Switching
Matrix)
QSE
(Switching
Matrix)
c
d
c
d
e
f
e
f
QRT
(IRT Portion)
a
b
QRT
(ORT Portion)
B
g
h
QSE/QSE Interface
B
Forward Cell Path
Backward BP/ACK Path
Figure 48. Basic Data Path Through the Switch
3.1.1 UTOPIA Interface
The QRT UTOPIA interface is compatible with the UTOPIA Level 1 specification revision 2.01
and the UTOPIA Level 2 specification in 16-bit mode with cell-level handshaking. An external
ATM clock must be provided to this interface with a frequency between 15 MHz and 50 MHz.
The lower bound is determined by the ATM_CLK failure detection circuitry. The receive and
transmit sides of the interface are independently configurable to operate in either single OC-12 or
multi-PHY fashion. The interface also provides several options in polling methods, so bandwidth,
servicing fairness, and response time are optimized for any given PHY layer device arrangement.
44
PMC [ PMC-SIERRA, INC ]
