Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
3.2.2.7 Highest Bandwidth Device Support in UTOPIA Level 2 Mode
The QRT UTOPIA Level-2 50 MHz interface was not designed to operate with any device
possessing a bandwidth greater than that of an OC-3. For higher bandwidth requirements,
the user must use the single-PHY UTOPIA Level-1 mode of operation.
3.2.3 Switch Fabric Fault Detection and Recovery Mechanisms
The QRT uses several mechanisms to ensure cell integrity through the switch fabric and to expe-
diently detect, isolate, and rectify fault conditions.
3.2.3.1 SOC Coding
SOC Coding — A special background pattern “0000111100001...” is generated on the
SOC at the ingress QRT and is propagated by the QSE. This background pattern is
checked at the egress QRT. If this pattern is inconsistent or missing, the forward cell path
is declared bad and the SE_INPUT_PORT_FAIL interrupt (refer to
“SE_INPUT_PORT_FAIL” on page 112) is asserted.
3.2.3.2 SOC Inversions
The SOC is indicated by an inversion of the background pattern. Also, the pattern is reset
so a valid SOC will always be followed by “000011110000...”. This pattern reset is
checked by the egress QRT, and if it is inconsistent, the forward path is declared bad and
the SE_INPUT_PORT_FAIL interrupt (refer to “SE_INPUT_PORT_FAIL” on page 112)
is asserted.
3.2.3.3 Redundant Cell Present Coding
The first nibble of each valid cell has a predetermined format. This format is checked as
the cell is received at the egress QRT. If the format is inconsistent, the forward cell path is
declared
bad
and
the
SE_INPUT_PORT_FAIL
interrupt
(refer
to
“SE_INPUT_PORT_FAIL” on page 112) is asserted. This also increases the robustness of
the cell presence detection, preventing an all-1s input from creating cells.
3.2.3.4 Idle Cell Pattern Checking
An idle cell at the ingress QRT has a predetermined format. This pattern is checked at the
egress QRT when the idle cell is received. If the format is inconsistent, the forward cell
path is declared bad and the SE_INPUT_PORT_FAIL interrupt (refer to
“SE_INPUT_PORT_FAIL” on page 112) is asserted.
3.2.3.5 Dropping Cells with Bad Header Parity
Odd parity is generated over the first 12 nibbles of every valid cell. The parity bit is
embedded in the twelfth nibble. Parity checking can be disabled by asserting the
PARITY_FAIL_DIS bit (refer to “PARITY_FAIL_DIS” on page 107). When parity
checking is enabled, cells with bad parity are dropped and a failure is reported to the
microprocessor via the TX_PARITY_FAIL flag (refer to “TX_PARITY_FAIL” on
page 111).
47
PMC [ PMC-SIERRA, INC ]
