Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
2.7 System Diagram of Internal QRT Blocks and External RAM
Figure 47 shows a system diagram of the internal QRT blocks and the external RAM.
50 MHz
100 MHz
66 MHz
RX DRAM
ABR RAM
Cell Buffer
Receive
DRAM
Control
ABR RAM
Control
Receive UTOPIA
Microprocessor
To QSE
RU RAM
RS RAM
Microprocessor
Interface
RSF RAM
RSC RAM
BP/Ack from QSE
BP/Ack to QSE
UTOPIA
Loopback
AL RAM
Control
AL RAM
CH RAM
Queue
Engine
CH RAM
Control
VO RAM
TSC RAM
TSF RAM
TS RAM
Transmit UTOPIA
TU RAM
From QSE
TX DRAM
Control
MC RAM
TX DRAM
Cell Buffer
50 MHz
100 MHz
66 MHz
Figure 47. System Diagram of Internal QRT Blocks and External RAM
43
PMC [ PMC-SIERRA, INC ]
