Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
3.1.2 Switch Fabric Interface
The switch fabric interface of the QRT has four nibble-wide, 50 or 66 MHz interfaces with back-
pressure to interface to QSEs (PM73488s). The device can avoid head-of-line blocking by receiv-
ing two forms of negative acknowledgment from the switch fabric. One form of negative
acknowledgment indicates congestion that is likely to be resolved on the next cell time. This is
termed a Mid-switch NACK (or Medium Negative ACKnowledgment - MNACK). When the
QRT receives an MNACK, it resends the same cell. The other form of negative acknowledgment
indicates congestion that is not likely to be resolved on the next cell time. This is termed Output
Negative ACKnowledgment (ONACK). When the QRT receives an ONACK, it skips to another
channel and sends a cell from that different channel.
3.2 Fault Detection and Isolation
The data transfers internally between the various RAMs and between the QRT and the QSE are
checked by the following mechanisms:
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Memory parity checking
UTOPIA interface fault detection and recovery mechanisms
Switch fabric fault detection and recovery mechanisms
3.2.1 Memory Parity Checking
The receive and transmit buffer SDRAMs are checked by multibit parity.
All external SRAMs have parity checking. The parity conditions are checked. There are
two kinds of flags (sticky and non-sticky) set for each of these parity error conditions. The
sticky error bits are set by the error and are cleared by the processor. The corresponding
non-sticky bits are used for debugging purposes.
3.2.2 UTOPIA Interface Fault Detection and Recovery Mechanisms
The QRT uses several mechanisms to ensure cell integrity through the UTOPIA interface and to
expediently detect, isolate, and rectify fault conditions.
3.2.2.1 Header Error Check (HEC)
The receive or ingress UTOPIA interface can be configured to perform a HEC calculation
using the CHK_HEC bit in the UTOPIA_CONFIG register (refer to section 7.2.11
“UTOPIA_CONFIG” starting on page 117). When a HEC failure is detected and checking
is enabled, an interrupt is signaled at the processor interface and the cell is dropped at the
UTOPIA interface. Some Segmentation And Reassembly (SAR) and Physical layer
(PHY) devices do not produce the correct HEC or use the HEC for other purposes. To
connect the QRT to these devices, clear the CHK_HEC bit.
3.2.2.2 Start Of Cell (SOC) Recovery
The receive UTOPIA interface is flexible when dealing with the SOC signal sent from the
PHY layer device to the QRT. The QRT can accept a delay of up to four ATM clock
cycles in the aligned SOC and data signals after assertion of the Receive UTOPIA ATM
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PMC [ PMC-SIERRA, INC ]
