Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Layer Enable signal (/RATM_READ_EN). The SOC signal can arrive anywhere within
this window and the data will be accepted. Customers will find this feature useful if glue
logic is used for special PHY layer device adaptations. If, however, the SOC signal arrives
after the four-cycle window, the QRT will dump the cell and enter recovery mode. Recov-
ery mode is implemented for both single and multi-PHY configurations and provides
robustness to the QRT in the event of a late SOC resulting from a reset PHY or a double
SOC resulting from renegade PHY devices. The recovery mode performs precession in
the ATM cell cycles that follow. This is necessary to bring a PHY device back into syn-
chronization for slotted cell-level handshaking. SOC recovery performs the same func-
tions for stuck-at faults in the SOC signal. When an SOC failure is detected, an interrupt is
signaled at the processor interface.
3.2.2.3 Transmit Watchdog
The QRT transmit or egress UTOPIA interface has a function called the “watchdog”. The
watchdog exists to protect the QRT VO queues from overflow if a PHY sink goes offline
or stops requesting cells. The watchdog can be configured in the UTOPIA_CONFIG reg-
ister in the processor interface (refer to “WD_TIME” on page 118). The watchdog can be
turned off or set to tolerate either OC-3-, DS1-, or DS0-level outputs. The watchdog oper-
ates by observing the liveliness of the Transmit UTOPIA ATM Layer Cell Available sig-
nals (TATM_CLAV(3:0)). If the QRT determines a PHY device has stopped accepting
cells, the cells intended for that PHY device are played out. Otherwise, if the PHY device
can accept these cells and the TATM_CLAV(3:0) signal dormancy is due to a stuck-at
fault, normal UTOPIA signaling at the lowest priority occurs whenever spare bandwidth is
available.
3.2.2.4 Transmit Parity
The transmit UTOPIA interface performs UTOPIA Level 2 odd parity calculation over the
Transmit UTOPIA ATM Layer Data signals (TATM_DATA(15:0)) for the PHY devices
to use in error checking.
3.2.2.5 ATM Clock Failure Detection
The UTOPIA interface contains an ATM clock failure detection circuit. The detection cir-
cuit samples the ATM clock with the high-frequency system clock and determines if the
ATM clock possess signal changes. If the clock failure detection circuit is tripped, an
interrupt is signaled at the processor interface.
3.2.2.6 Receive Cell Available Signal Stuck at 1
When a PHY interface device’s cell available signal is stuck at 1, the receive UTOPIA
Level 2 interface limits the PHY to approximately one-half the receive side QRT band-
width. This condition can result from a floating cell available line and should be avoided
by designing pull-down resistors for the cell available lines. In the transmit direction, this
is not such an issue, because the cell service is dependent on the presence of a cell bound
for that PHY device. However, this condition should be minimized in the transmit direc-
tion also.
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PMC [ PMC-SIERRA, INC ]
