欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM73487 参数 Datasheet PDF下载

PM73487图片预览
型号: PM73487
PDF下载: 下载PDF文件 查看货源
内容描述: 622 Mbps的ATM流量管理设备 [622 Mbps ATM Traffic Management Device]
分类和应用: 异步传输模式ATM
文件页数/大小: 251 页 / 2936 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM73487的Datasheet PDF文件第106页浏览型号PM73487的Datasheet PDF文件第107页浏览型号PM73487的Datasheet PDF文件第108页浏览型号PM73487的Datasheet PDF文件第109页浏览型号PM73487的Datasheet PDF文件第111页浏览型号PM73487的Datasheet PDF文件第112页浏览型号PM73487的Datasheet PDF文件第113页浏览型号PM73487的Datasheet PDF文件第114页  
Released  
Datasheet  
PM73487 QRT  
PMC-Sierra, Inc.  
PMC-980618  
Issue 3  
622 Mbps ATM Traffic Management Device  
7 MICROPROCESSOR PORTS  
7.1 Microprocessor Ports Summary  
NOTES:  
The external /RESET signal resets all microprocessor write ports to 0 when asserted.  
All ports marked as “Reserved” must be initialized to 0 (unless otherwise indicated) at initial setup.  
Software modifications to these locations after setup may cause incorrect operation.  
All read/write port bits marked “Not used” must be written with the value 0 to maintain software com-  
patibility with future versions.  
Most read-only bits marked “Not used” are driven with a 0; however, some may have an unpredictable  
value on reads. Therefore, all read-only bits marked “Not used” should be masked by the software on  
reads to maintain compatibility with future versions.  
Table 23. Microprocessor Ports Summary  
Byte  
Long  
Read or  
Write  
Name  
Description  
Address Address  
0h  
4h  
0h  
1h  
REVISION  
RESET  
R
Contains the device part number and revision.  
Resets the device, except the microprocessor interface.  
Define various test/diagnostic functions.  
Defines the SRAM configuration.  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
8h  
2h  
TEST_CONFIG  
Ch  
3h  
SRAM_CONFIG  
SWITCH_CONFIG  
RAM BIST RESULT  
Not used  
10h  
14h  
14h-18h  
1Ch  
4h  
Defines the type of switch fabric.  
5h  
RAM BIST completion result  
5h-6h  
7h  
Set to 0 for software compatibility with future devices.  
MARKED_CELLS_COUNT  
Indicates the number of cells modulo (mod) 16 that had  
Tag(9,1) set to 1, sent to or from the switch fabric.  
20h  
24h  
8h  
9h  
CONDITION_PRES_BITS  
CONDITION_LATCH_BITS  
INTR_MASK  
R
Defines the condition of present bits.  
Defines the condition of latch bits.  
Defines the interrupt mask bits.  
R
28h  
Ah  
R/W  
R/W  
R/W  
R/W  
R/W  
2Ch-3Ch  
40h  
Bh-Fh  
10h  
11h  
12h  
Reserved  
Do not initialize.  
UTOPIA_CONFIG  
UT_PRIORITY  
Defines the mode of the UTOPIA interface.  
Indicates the priority of each virtual input/output.  
44h  
48h  
UT_ENABLE  
Enables whether the polling results from the PHY layer  
device will be considered during the UTOPIA PHY  
selection mechanism. Also sets the number of devices  
to be polled when standard polling is used.  
4Ch  
50h  
13h  
14h  
TX_UT_STAT  
R
R/W  
R
Indicates the transmit UTOPIA status.  
TX_UT_WD_ALIVE  
Indicates the transmit UTOPIA watchdog liveness.  
54h-7Fh  
15h-1Fh Not used  
Driven with a 0. Mask on reads to maintain compatibil-  
ity with future versions.  
80h  
20h RX_CELL_START_ALIGN  
R/W  
Contains alignment value for the internal RxCellStart  
signal from the external RX_CELL_START.  
98  
 复制成功!