S/UNI®-JET Data Sheet
Released
Register 3A4H: PRGD Error Insertion Register
Bit
Type
Function
Unused
Unused
Unused
Unused
EVENT
EIR[2]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
0
0
0
0
R/W
R/W
R/W
R/W
EIR[1]
EIR[0]
EVENT
A low-to-high transition on the EVENT bit causes a single bit error to be inserted in the
generated pattern. This bit must be cleared and set again for a subsequent error to be inserted.
EIR[2:0]
The EIR[2:0] bits control the insertion of a programmable bit error rate as indicated in Table
26:
Table 26 PRGD Generated Bit Error Rate Configurations
EIR[2:0]
000
Generated Bit Error Rate
No errors inserted
001
-1
-2
-3
-4
-5
-6
-7
10
10
10
10
10
10
10
010
011
100
101
110
111
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
243
PMC [ PMC-SIERRA, INC ]
