S/UNI®-JET Data Sheet
Released
Register 383H: TXCP-50 Interrupt Enable/Status
Bit
Type
R/W
R/W
R/W
Function
TPRTYE
FOVRE
TSOCE
Unused
Unused
TPRTYI
FOVRI
Default
0
0
0
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
TSOCI
TSOCI
The TSOCI bit is set high when the TSOC input is sampled high during any position other
than the first word of the selected data structure. The write address counter is reset to the first
word of the data structure when TSOC is sampled high. This bit is reset immediately after a
read to this register.
FOVRI
The FOVRI bit is set high when an attempt is made to write into the FIFO when it is already
full. This bit is reset immediately after a read to this register
TPRTYI
The TPRTYI bit indicates if a parity error was detected on the TDAT input bus. When logic
one, the TPRTYI bit indicates a parity error over the active TDAT bus. The active TDAT bus
is TDAT[15:0] when ATM8 is tied low and is TDAT[7:0] when ATM8 is tied high. This bit is
cleared when this register is read. Odd or even parity is selected using the TPTYPE bit.
TSOCE
The TSOCE bit enables the generation of an interrupt when the TSOC input is sampled high
during any position other than the first word of the selected data structure. When TSOCE is
set to logic one, the interrupt is enabled.
FOVRE
The FOVRE bit enables the generation of an interrupt due to an attempt to write the FIFO
when it is already full. When FOVRE is set to logic one, the interrupt is enabled.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
216
PMC [ PMC-SIERRA, INC ]
