S/UNI®-JET Data Sheet
Released
Register 381H: TXCP-50 Configuration 2
Bit
Type
Function
Unused
Unused
Unused
TCAINV
FIFODP[1]
FIFODP[0]
DHCS
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
HCSCTLEB
HCSCTLEB
The active low HCS control enable, HCSCTLEB bit enables the XORing of the HCS Control
byte with the generated HCS. When set to logic zero, the HCS Control byte provided in the
third word of the 27-byte word data structure is XORed with the generated HCS. When set to
logic one, XORing is disabled and the HCS Control byte is ignored.
DHCS
The DHCS bit controls the insertion of HCS errors for diagnostic purposes. When DHCS is
set to logic one, the HCS octet is inverted prior to insertion in the synchronous payload
envelope. DHCS takes effect unconditionally regardless of whether a null/unassigned cell is
being transmitted or whether the HCS octet has been read from the FIFO. DHCS occurs after
any error insertion caused by the Control Byte in the 27-byte word data structure.
FIFODP[1:0]
The FIFODP[1:0] bits determine the transmit FIFO cell depth at which TCA and DTCA[x]
de-assert. FIFO depth control may be important in systems where the cell latency through the
TXCP-50 must be minimized. When the FIFO is filled to the specified depth, the transmit cell
available signal, TCA (and DTCA[x]) is de-asserted. Note: Regardless of what fill level
FIFODP[1:0] is set to, the transmit cell processor can store four complete cells. The
selectable FIFO cell depths are shown in Table 23:
Table 23 TXCP-50 FIFO Depth Configurations
FIFODP[1]
FIFODP[0]
FIFO DEPTH
4 cells
3 cells
2 cells
1 cell
0
0
1
1
0
1
0
1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
213
PMC [ PMC-SIERRA, INC ]
