S/UNI®-JET Data Sheet
Released
HCSB
The active low HCSB bit enables the internal generation and insertion of the HCS octet into
the transmit cell stream. When HCSB is logic zero, the HCS is generated and inserted
internally. When the HCSB and DS27_53 register bits are logic one, the HCS octet read from
the transmit FIFO is inserted transparently into the transmit cell stream, but the TXCP-50 will
still generate and insert the HCS octet for idle cells. If HCSB is logic one and the 26-byte
word data structure is selected (DS27_53 is logic zero), then no HCS octet is inserted in the
transmit data stream.
HCSDQDB
The HCSDQDB bit controls the cell header octets included in the HCS calculation. When a
logic one is written to HCSDQDB, header octets two, three, and four are included in the HCS
calculation as required by IEEE-802.6 DQDB specification. When a logic zero is written to
HCSDQDB, all four header octets are included in the HCS calculation as required by the
ATM Forum UNI specification and ITU-T Recommendation I.432.
HSCR
The Header Scramble enable bit, HSCR, enables scrambling of the ATM five octet header
along with the payload. When set to logic one, the ATM header and payload are both
scrambled. When set to logic zero, the header is left unscrambled and payload scrambling is
determined by the DSCR bit.
TCALEVEL0
The active high TCA (and DTCA[x]) level 0 bit, TCALEVEL0 determines what output TCA
(and DTCA[x]) indicates when it de-asserts (transitions to logic zero if TCAINV is logic
zero, or transitions to logic one if TCAINV is logic one).
When TCALEVEL0 is set to logic one, TCA (and DTCA[x]) indicates that the transmit FIFO
is full and can accept no more writes. DTCA[x] and TCA, if polled, will de-assert on the
rising TFCLK edge when Payload byte 47 (ATM8=1) or Payload word 23 (ATM8=0) is
sampled.
When TCALEVEL0 is set to logic zero, TCA (and DTCA[x]) indicates that the transmit
FIFO is near full. DTCA[x] and TCA, if polled, will de-assert on the rising TFCLK edge
when Payload byte 43 (ATM8=1) or Payload word 19 (ATM8=0) is sampled.
TPTYP
The TPTYP bit selects even or odd parity for input TPRTY. When set to logic one, input
TPRTY is the even parity bit for the TDAT input bus. When set to logic zero, input TPRTY is
the odd parity bit for the TDAT input bus. When ATM8 is set to logic one, the input bus
consists of TDAT[7:0]. When ATM8 is logic zero, the input bus consists of TDAT[15:0].
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
212
PMC [ PMC-SIERRA, INC ]
