S/UNI®-JET Data Sheet
Released
Register 384H: TXCP-50 Idle Cell Header Control
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
GFC[3]
GFC[2]
GFC[1]
GFC[0]
PTI[2]
PTI[1]
PTI[0]
CLP
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
1
CLP
The CLP bit contains the eighth bit position of the fourth octet of the idle/unassigned cell
pattern. Cell rate decoupling is accomplished by transmitting idle cells when the TXCP-50
detects that no outstanding cells exist in the transmit FIFO.
PTI[3:0]
The PTI[3:0] bits contains the fifth, sixth, and seventh bit positions of the fourth octet of the
idle/unassigned cell pattern. Idle cells are transmitted when the TXCP-50 detects that no
outstanding cells exist in the transmit FIFO.
GFC[3:0]
The GFC[3:0] bits contain the first, second, third, and fourth bit positions of the first octet of
the idle/unassigned cell pattern. Idle/unassigned cells are transmitted when the TXCP-50
detects that no outstanding cells exist in the transmit FIFO. The all-zeros pattern is
transmitted in the VCI and VPI fields of the idle cell.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
218
PMC [ PMC-SIERRA, INC ]
