S/UNI®-JET Data Sheet
Released
Register 380H: TXCP-50 Configuration 1
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
TPTYP
TCALEVEL0
HSCR
HCSDQDB
HCSB
HCSADD
DSCR
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
0
0
FIFORST
FIFORST
The FIFORST bit is used to reset the four cell transmit FIFO. When FIFORST is set to logic
zero, the FIFO operates normally. When FIFORST is set to logic one, the FIFO is
immediately emptied and ignores writes. The FIFO remains empty and continues to ignore
writes until a logic zero is written to FIFORST. Null/unassigned cells are transmitted until a
subsequent cell is written to the FIFO.
See Section 13.9on resetting the receive and transmit FIFOs.
DSCR
The DSCR bit controls the scrambling of the cell payload. When DSCR is a logic one, cell
payload scrambling is disabled. When DSCR is a logic zero, payload scrambling is enabled.
In the case where HSCR is logic one, the payload will be scrambled (along with the header)
regardless of the setting of the DSCR bit.
HCSADD
6
4
2
The HCSADD bit controls the addition of the coset polynomial, x +x +x +1, to the HCS
octet prior to insertion in the synchronous payload envelope. When HCSADD is a logic one,
the polynomial is added, and the resulting HCS is inserted. When HCSADD is a logic zero,
the polynomial is not added, and the unmodified HCS is inserted. HCSADD takes effect
unconditionally regardless of whether a null/unassigned cell is being transmitted or whether
the HCS octet has been read from the FIFO.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
211
PMC [ PMC-SIERRA, INC ]
