S/UNI®-JET Data Sheet
Released
Register 36DH: RXCP-50 Receive Cell Counter (MSB)
Bit
Type
Function
Unused
Unused
Unused
Unused
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Unused
R
R
R
RCELL[18]
RCELL[17]
RCELL[16]
RCELL[18:0]
The RCELL[18:0] bits indicate the number of cells received and written into the receive
FIFO during the last accumulation interval. Cells received and filtered due to HCS errors or
Idle cell matches are not counted. The counter should be polled every second to avoid
saturation. The contents of these registers are valid after 24 RCLK periods containing cell
header or payload data (line or PLCP overhead periods do not count) after a transfer is
triggered by a write to one of RXCP-50's performance monitor counters (Registers 369H –
371H) or to the S/UNI-JET Identification, Master Reset, and Global Monitor Update Register
(006H).
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
208
PMC [ PMC-SIERRA, INC ]
