S/UNI®-JET Data Sheet
Released
Register 363H: RXCP-50 Interrupt Enables and Counter Status
Bit
Type
R
R
Function
XFERI
OVR
Unused
XFERE
OOCDE
HCSE
FOVRE
LCDE
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
LCDE
The LCDE bit enables the generation of an interrupt due to a change in the LCD state. When
LCDE is set to logic one, the interrupt is enabled.
FOVRE
The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition.
When FOVRE is set to logic one, the interrupt is enabled.
HCSE
The HCSE bit enables the generation of an interrupt due to the detection of a corrected or an
uncorrected HCS error. When HCSE is set to logic one, the interrupt is enabled.
OOCDE
The OOCDE bit enables the generation of an interrupt due to a change in cell delineation
state. When OOCDE is set to logic one, the interrupt is enabled.
XFERE
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the RXCP-50 Count Registers. When XFERE is set
to logic one, the interrupt is enabled.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
197
PMC [ PMC-SIERRA, INC ]
