S/UNI®-JET Data Sheet
Released
Register 361H: RXCP-50 Configuration 2
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
CCDIS
HCSPASS
IDLEPASS
IN52
ALIGN[1]
ALIGN[0]
HCSFTR[1]
HCSFTR[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
HCSFTR[1:0]
The HCS filter bits, HCSFTR[1:0] indicate the number of consecutive error-free cells
required, while in detection mode, before reverting back to correction mode. Refer to Table
20.
Table 20 RXCP-50 HCS Filtering Configurations
HCSFTR[1:0]
00
Cell Acceptance Threshold
One ATM cell with correct HCS before resumption of cell acceptance. This cell
is accepted.
01
10
11
Two ATM cells with correct HCS before resumption of cell acceptance. The last
cell is accepted.
Four ATM cells with correct HCS before resumption of cell acceptance. The last
cell is accepted.
Eight ATM cells with correct HCS before resumption of cell acceptance. The
last cell is accepted.
ALIGN[1:0]
ALIGN[1:0] configures the RXCP-50 to perform cell delineation based on byte, nibble, or bit
wide search algorithms when ATM Direct Mapping is used. Cell alignment is relative to
overhead bits in the serial input data stream. The ALIGN[1:0] bits are valid only if ATM
direct mapping is used. PLCP framing must be disabled. The Recommended settings for DS3,
E3, and J2 are shown in Table 21.
Table 21 RXCP-50 Cell Delineation Algorithm Base
ALIGN[1:0]
Cell Delineation Algorithm base
Bit
Nibble (DS3)
Byte (E3,J2, E1, T1)
Unused
00
01
10
11
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
193
PMC [ PMC-SIERRA, INC ]
