S/UNI®-JET Data Sheet
Released
IN52
The IN52 bit defines the number of bytes contained in incoming cells. When IN52 is a logic
zero, incoming cells are 53-bytes in length. When IN52 is a logic one, incoming cells are 52-
bytes in length. In order for ATM cell delineation to function properly, incoming cells must be
53-bytes in length including a valid HCS byte. The HCS byte can be stripped off on the
Utopia side using the DS27_53 register bit. If the S/UNI QJET is operating in PPP mode,
incoming "cells" may be composed of 52 or 53 bytes without an HCS byte. In this case, the
CCDIS register bit should be set to disable cell delineation, and the DS27_53 register bit
should be set so that it is consistent with IN52.
IDLEPASS
The IDLEPASS bit controls the function of the Idle Cell filter. When IDLEPASS is written
with a logic zero, all cells that match the Idle Cell Header Pattern and Idle Cell Header Mask
are filtered out. When IDLEPASS is a logic one, the Idle Cell Header Pattern and Mask
Registers are ignored. The default state of this bit and the bits in the Idle Cell Header Mask
and Idle Cell Header Pattern Registers enable the dropping of idle cells.
HCSPASS
The HCSPASS bit controls the dropping of cells based on the detection of an uncorrectable
HCS error. When HCSPASS is a logic zero, cells containing an uncorrectable HCS error are
dropped. When HCSPASS is a logic one, cells are passed to the receive FIFO regardless of
errors detected in the HCS. Additionally, the HCS verification finite state machine never exits
the correction mode.
Regardless of the programming of this bit, cells are always dropped while the cell delineation
state machine is in the 'HUNT' or 'PRESYNC' states unless the CCDIS bit in this register is
set to logic one.
CCDIS
The CCDIS bit can be used to disable all cell filtering and cell delineation. All payload data
read by the RXCP-50 is passed into its FIFO without the requirement of having to find cell
delineation first. If PLCP framing is disabled, then alignment of the data read out of the ATM
interface with respect to the line overhead is set by the ALIGN[1:0] bits of this register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
194
PMC [ PMC-SIERRA, INC ]
